UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 809

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) UARTCn control register 1 (UCnCTL1)
(3) UARTCn control register 2 (UCnCTL2)
For details, see 17.7 (2) UARTCn control register 1 (UCnCTL1).
For details, see 17.7 (3) UARTCn control register 2 (UCnCTL2).
Remarks 1. For details of parity, see 17.6.9 Parity types and operations.
• This register is rewritten only when the UCnPWR bit = 0 or the UCnTXE bit = the
• If “Reception with 0 parity” is selected during reception, a parity check is not performed.
• When transmission and reception are performed in the LIN format, clear the
• This register can be rewritten only when the UCnPWR bit = 0 or the UCnTXE bit =
• When transmission and reception are performed in the LIN format, set the UCnCL
This register can be rewritten only when the UCnPWR bit = 0 or the UCnTXE bit =
the UCnRXE bit = 0.
• This register can be rewritten only when the UCnPWR bit = 0 or the UCnTXE bit =
• When transmission and reception are performed in the LIN format, set the UCnDIR
UCnPS1
UCnDIR
UCnCL
UCnSL
UCnRXE bit = 0.
Therefore, the UCnSTR.UCnPE bit is not set.
UCnPS1 and UCnPS0 bits to 00.
the UCnRXE bit = 0.
bit to 1.
the UCnRXE bit = 0.
bit to 1.
0
1
0
1
0
1
0
0
1
1
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
7 bits
8 bits
1 bit
2 bits
MSB-first transfer
LSB-first transfer
2. n = 0 to 5 (V850ES/JH3-E)
UCnPS0
Specification of data character length of 1 frame of transmit/receive data
n = 0 to 7 (V850ES/JJ3-E)
0
1
0
1
Parity selection during transmission Parity selection during reception
No parity output
0 parity output
Odd parity output
Even parity output
Specification of length of stop bit for transmit data
User’s Manual U19601EJ2V0UD
Transfer direction selection
Reception with no parity
Reception with 0 parity
Odd parity check
Even parity check
(2/2)
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