UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 1496

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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MDIO
MDIO
MDC
MDC
(c) SCAN command
A 32-bit preamble, 2-bit start bit field, and 2-bit opcode, which indicates whether a register in the PHY
device is read or written, are automatically appended to the serial management frame. PHYAD and
REGAD indicate the address of the externally connected PHY device and the address of a register in that
PHY device respectively. The values set to the MADR.FIAD and RGAD bits are appended to PHYAD and
REGAD, respectively.
The Ethernet controller serially outputs data from the preamble to REGAD, and after a 2-bit turnaround,
the data set to the CTLD bits of the MWTD register is output for a write access. For a read access, serial
data is input by the MDI signal and written to the MRDD.PRSD bit.
While the MDO signal is being output, the MDOEN signal is asserted to 1.
The Ethernet controller has a SCAN command to successively read a specific PHY register. When the
MCMD.SCANC bit is set to 1, read accesses are generated one after another.
MRDD.PRSD bit, the specific PHY register can be polled.
Remark
Remark
PRE
PRE
Figure 23-13. Timing of MII Management Interface Signal (Write Access)
Figure 23-14. Timing of MII Management Interface Signal (Read Access)
Setting conditions: PHYAD = 01H, REGAD = 01H, CTLD = 0001H
Setting conditions: PHYAD = 01H, REGAD = 01H, CTLD = 8001H
ST
ST
CHAPTER 23 ETHERNET CONTROLLER
OP
OP
User’s Manual U19601EJ2V0UD
PHYAD
PHYAD
REGAD
REGAD
TA
TA
DATA
DATA
By reading the