UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 762

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(5) Reception timeout interrupt request signal (INTUBnTITO)
(a) Single mode
(b) FIFO mode
Cannot be used.
The reception timeout interrupt request signal is generated if data is stored in receive FIFO when the next
data does not come (start bit is not detected) even after the next data reception wait time specified by the
UBnFIC1.UBnTC4 to UBnFIC1.UBnTC0 bits has elapsed, when the timeout counter function is used
(UBnFIC1.UBnTCE bit = 1).
The reception timeout interrupt request signal is not generated while reception is disabled.
If receive data of the number set as the trigger by the UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits is not
received, the timing of reading the number of receive data less than the specified number can be set by
the reception timeout interrupt request signal.
Since the timeout counter starts counting at start bit detection, a receive timeout interrupt request signal
does not occur if data of 1 character has not been received.
Remark
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
n = 0, 1
User’s Manual U19601EJ2V0UD