UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 411

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Operation timing in one-shot pulse output mode
(TIAB00 pin input)
External trigger input
INTTABnCC0 signal
INTTABnCCk signal
(only when software
TABnCCR0 register
TABnCCRk register
TOABn0 pin output
TOABnk pin output
(a) Notes on rewriting TABnCCRm register
trigger is used)
16-bit counter
To change the set value of the TABnCCRm register to a smaller value, stop counting once, and then
change the set value.
If the value of the TABnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter
may overflow.
TABnCE bit
Note TAB1: TRGAB1 pin
When the TABnCCR0 register is rewritten from D
where D
counter is greater than D
value is greater than D
rewritten and compared with the count value. The counter counts up to FFFFH and then counts up again
from 0000H. When the count value matches D
asserts the TOABnk pin. When the count value matches D
signal, deasserts the TOABnk pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the
one-shot pulse that is originally expected.
Remark
FFFFH
0000H
Note
00
k = 1 to 3,
n = 0, 1
> D
01
and D
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Delay
(D
01
k0
k0
k1
and less than D
)
Active level width
> D
D
(D
k0
and less than D
00
k1
− D
, if the TABnCCRk register is rewritten when the count value of the 16-bit
D
k0
D
User’s Manual U19601EJ2V0UD
k0
D
00
+ 1)
00
00
, each set value is reflected as soon as the register has been
k0
(10000H + D
and if the TABnCCR0 register is rewritten when the count
D
k0
k1
00
Delay
, the counter generates the INTTABnCCk signal and
to D
D
01
k1
00
)
and the TABnCCRk register from D
01
, the counter generates the INTTABnCC0
Active level width
D
(D
k1
01
− D
D
k1
k1
D
+ 1)
01
D
01
Delay
(D
k1
Active level width
D
)
(D
k1
01
− D
k1
D
+ 1)
01
k0
to D
409
k1