UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 752

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

750
Cautions 3. Do not perform the following operations when debugging a system that uses the single
UBnRXAP
(n = 0, 1)
(n = 0, 1)
UBnRX
After reset: FFH
After reset: 00FFH
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
mode.
• Setting a break for an instruction immediately after the UBnRX register is read
• Setting a break before DMA transfer with the UBnRX register specified as the transfer
• Setting a break before end of reception of the next data after reception of data and
If any of these operations is performed, an overrun error may occur during the
subsequent reception.
source is ended
reading the UBnRX register, and checking the UBnRX register in the I/O register
window of the debugger
UBnRD7
UBnRD7 UBnRD6 UBnRD5 UBnRD4 UBnRD3 UBnRD2 UBnRD1 UBnRD0
UBnPEF
UBnFEF
UBnRD7 to
UBnRD0
•
•
•
•
The UBnPEF bit is valid only in the FIFO mode (UBnFIC0.UBnMOD bit = 1), and
is invalid in the single mode (UBnFIC0.UBnMOD bit = 0).
The operation of the UBnPEF bit differs depending on the set values of the
UBnCTL0.UBnPS1 and UBnCTL0.UBnPS0 bits.
The UBnFEF bit is valid only in the FIFO mode (UBnFIC0.UBnMOD bit = 1), and
is invalid in the single mode (UBnFIC0.UBnMOD bit = 0).
Only the first bit of the stop bits of the receive data is checked, regardless of the
stop bit length.
15
7
0
7
0
1
0
1
UBnRD6
No parity error
Parity error occurs (when reception completed).
No framing error
Framing error occurs (wheng reception completed).
Stores receive data.
R
R
14
6
0
6
Address: UB0RX FFFFFB86H, UB1RX FFFFFBA6H
Address: UB0RXAP FFFFFB86H, UB1RXAP FFFFFBA6H
User’s Manual U19601EJ2V0UD
UBnRD5
13
5
0
5
UBnRD4
12
4
0
4
Framing error flag
Parity error flag
UBnRD3
11
3
0
3
UBnRD2
10
2
0
2
UBnRD1
UBnPEF UBnFEF
1
9
1
UBnRD0
0
8
0