UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 1490

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(a) When a frame is received, data is stored in the receive FIFO.
(b) When the amount of data in the receive FIFO exceeds the value indicated by FLOWTHR, a pause control frame is transmitted.
(c) The data in the receive FIFO is read by DMA.
(d) When the amount of data in the receive FIFO falls below the value indicated by ZPTHR, a zero pause control frame is transmitted.
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Remark The shaded part of the receive FIFO in the above figures indicates the quantity of the data in the
receive FIFO. If does not indicate how data is actually stored.
DMAC
DMAC
DMAC
DMAC
ZPTHR
ZPTHR
ZPTHR
ZPTHR
CHAPTER 23 ETHERNET CONTROLLER
Receive FIFO
Receive FIFO
Receive FIFO
Receive FIFO
Figure 23-10. Flow Control
User’s Manual U19601EJ2V0UD
Zero pause control
FLOWTHR
FLOWTHR
FLOWTHR
FLOWTHR
frame request
Pause control
frame request
MAC
MAC
MAC
MAC
The other terminal that has received the
zero pause control frame stops pausing
at that point and transmits the next frame.
During this operation, the other terminal
defers transmission of the next frame
until the pause period has elapsed.
Frame reception
Pause control
frame reception
Frame reception
Zero pause control
frame reception