UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 1384

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1382
15 to 0
(10) VLTP: VLAN type register
Bit
This register is used to specify the operation to be performed on a VLAN frame.
Access
Address
Default value 0000 0000H. This register is cleared to its default value by all types of resets.
Caution Be sure to set bits 31 to 16 to “0”.
VLTP[15:0]
VLTP15
VLTP7
R/W
R/W
31
23
15
Name
R
R
0
0
7
This register can be read and written in 32-bit units.
002E 0064H
VLTP14
VLTP6
VLAN frame operation
These bits specify the operation to be performed or a VLAN frame (refer to 23.5.4 (3) Operations
related to VLAN frame).
During reception: The value of VLTP[15:0] is compared with the value of the TPID field (2 bytes
following the source address) of a frame to detect a VLAN frame.
During transmission: If the value of the VLAN field matches the value of VLTP[15:0] when the
MACC2.APD bit is set to 1, PAD is appended to the VLAN frame.
R/W
R/W
30
22
14
R
R
0
0
6
VLTP13
VLTP5
CHAPTER 23 ETHERNET CONTROLLER
R/W
R/W
29
21
13
R
R
0
0
5
User’s Manual U19601EJ2V0UD
VLTP12
VLTP4
R/W
R/W
28
20
12
R
R
0
0
4
VLTP11
VLTP3
R/W
R/W
27
19
11
R
R
0
0
3
Description
VLTP10
VLTP2
R/W
R/W
26
18
10
R
R
0
0
2
VLTP9
VLTP1
R/W
R/W
25
17
R
R
0
0
9
1
VLTP8
VLTP0
R/W
R/W
24
16
R
R
0
0
8
0