UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 823

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.6.3 SBF transmission
SBF transmission is started by setting (to 1) the SBF transmission trigger (UCnOPT0.UCnSTT bit).
is output. A transmission enable interrupt request signal (INTUCnT) is generated upon SBF transmission start.
Following the end of SBF transmission, the UCnSTT bit is automatically cleared. Thereafter, the UART transmission
mode is restored.
transmission trigger (UCnSTT bit) is set.
When the UCnCTL0.UCnPWR bit = UCnCTL0.UCnTXE bit = 1, the transmission enabled status is entered, and
Thereafter, a low level the width of bits 13 to 20 specified by the UCnOPT0.UCnSLS2 to UCnOPT0.UCnSLS0 bits
Transmission is suspended until the data to be transmitted next is written to the UCnTX register, or until the SBF
TXDCn
INTUCnT
interrupt
Remark
Setting of UCnSTT bit
n = 0 to 5 (V850ES/JH3-E)
n = 0 to 7 (V850ES/JJ3-E)
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
1
2
Figure 17-13. SBF Transmission
3
User’s Manual U19601EJ2V0UD
4
5
6
7
8
9
10
11
12
13
Stop
bit
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