UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 1515

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

RXDP/TXDP
(7) Byte alignment and word boundary
When the beginning of a descriptor chain is specified by a link pointer, a ring buffer is configured. In the case
of a ring buffer, the Ethernet controller generates the RECI or TECI interrupt when a descriptor whose U bit is
set is read in the same manner as it detects an end of chain, and stops DMA.
Caution Handling of U bit
A descriptor must be word-aligned but the data buffer can be set at a byte-aligned address.
The Ethernet controller automatically identifies an address, executes single transfer up to a word boundary or
transfer of a word of undefined length up to the burst boundary, and then executes burst transfer.
(E bit = 0 indicates link to next descriptor)
The U bit set to a transmit descriptor indicates that transmission of the descriptor is
completed, and the CPU can set a new descriptor by clearing the U bit.
However, a receive descriptor may be updated later by status write back or error occurrence
even if the U bit is set. Therefore, a new descriptor cannot be set unless completion of
packet reception is confirmed. If the E bit is set, however, it indicates that packet reception
has been completed and therefore, that the descriptor chain can be set as a new descriptor.
Figure 23-25. Overview of Ring Buffer Formed by Descriptor Chain
Buffer descriptor [1]
Buffer descriptor [2]
Buffer descriptor [a-1]
Buffer descriptor [a]
Link pointer
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•
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CHAPTER 23 ETHERNET CONTROLLER
Memory map
User’s Manual U19601EJ2V0UD
: Packet
: Empty
Data buffer [a-1]
Data buffer [1]
Data buffer [2]
Data buffer [a]
Memory map
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