UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 880
UPD70F3785GJ-GAE-AX
Manufacturer Part Number
UPD70F3785GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3785GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Company:
Part Number:
UPD70F3785GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
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INTCEnT interrupt
(14) Delay control of transmission/reception completion interrupt (INTCEnT)
SCKEn (output)
SOEn (output)
Figure 18-12. Delay Control of Transmission/Reception Completion Interrupt (INTCEnT):
Note If the CEnCTL0.CEnTMS bit is set to 1 in the continuous mode (CEnCTL0.CEnTMS bits = 1), the
Remark
SIEn (input)
In the master mode (CEnCTL1.CEnCKS2 to CEnCTL1.CEnCKS0 bits = other than 111), occurrence of the
transmission/reception completion interrupt (INTCEnT) can be delayed by half a clock (1/2 serial clock),
depending on the setting (1) of the CEnCTL0.CEnTMS bit. The CEnSIT bit is valid only in the master mode.
In the slave mode (CEnCTL1.CEnCKS2 to CEnCTL1.CEnCKS0 bits = 111), setting the CEnSIT bit to 1 is
prohibited (even if set, the INTCEnT interrupt is not affected).
Caution If the CEnCTL0.CEnTMS bit is set to 1 in the continuous mode (CEnCTL0.CEnTMS bit = 1),
INTCEnT interrupt is not output at the end of data other than the last data set by the
CEnCTL3.CEnSFN3 to CEnCTL3.CEnSFN0 bits, but a delay of half a clock (1/2 serial clock) can be
inserted between each data transfer.
n = 0, 1
the INTCEnT interrupt is not output at the end of data other than the last data set by the
CEnCTL3.CEnSFN3 to CEnCTL3.CEnSFN0 bits, but a delay of half a clock (1/2 serial clock)
can be inserted between each data transfer.
CEnCTL0.CEnSIT Bit = 1, CEnCKP, CEnDAP Bits = 00,
CEnCTL2.CEnDLS3 to CEnCTL2.CEnDLS0 Bits = 1000 (Transfer Data Length: 8 Bits)
CHAPTER 18 CLOCKED SERIAL INTERFACE E WITH FIFO (CSIE)
DO7
DI7
DO6
DI6
User’s Manual U19601EJ2V0UD
DO5
DI5
DO4
DI4
DO3
DI3
DO2
DI2
DO1
DI1
Delay
DO0
DI0
Delay
Note
DO7
DI7
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