UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 838

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

836
Remark f
Baud Rate
1000000
1250000
2000000
2500000
3000000
153600
312500
625000
19200
31250
38400
76800
(bps)
1200
2400
4800
9600
To set the baud rate, perform the following calculation for setting the UCnCTL1 and UCnCTL2 registers (when
using internal clock).
<1> Set k to fxx/2/(2 × target baud rate) and m to 0.
<2> If k is 256 or greater (k ≥ 256), reduce k to half (k/2) and increment m by 1 (m + 1).
<3> Repeat Step <2> until k becomes less than 256 (k < 256).
<4> Round off the first decimal point of k to the nearest whole number.
<5> Set the value of m to UCnCTL1 register and the value of k to the UCnCTL2 register.
Example: When f
The representative examples of baud rate settings are shown below.
300
600
If k becomes 256 after round-off, perform Step <2> again to set k to 128.
ERR: Baud rate error (%)
n = 0 to 5 (V850ES/JH3-E)
n = 0 to 7 (V850ES/JJ3-E)
XX
UCnC
:
08H
07H
06H
05H
04H
03H
02H
01H
01H
00H
00H
00H
00H
00H
00H
00H
00H
00H
TL1
<1> k = 50,000,000/2/(2 × 153,600) = 81.380…, m = 0
<2>, <3> k = 81.380… < 256, m = 0
<4> Set value of UCnCTL2 register: k = 81 = 51H, set value of UCnCTL1 register: m = 0
Actual baud rate = 50,000,000/2/(2 × 81)
Baud rate error = {50,000,000/2/(2 × 81 × 153,600) − 1} × 100
Main clock frequency
f
XX
UCnC
A3H
A3H
A3H
A3H
A3H
A3H
A3H
C0H
A3H
A3H
0DH
0AH
51H
28H
14H
06H
05H
04H
TL2
= 50 MHz
XX
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
= 50 MHz and target baud rate = 153,600 bps
ERR (%)
−0.15
−0.15
−0.15
−0.15
−0.15
−0.15
−0.15
−0.15
−0.15
−0.15
−3.85
0.47
0.00
0.00
0.00
4.17
0.00
4.17
Table 17-4. Baud Rate Generator Setting Data
= 154,321 [bps]
= 0.469 [%]
UCnC
08H
07H
06H
05H
04H
03H
02H
01H
01H
00H
00H
00H
00H
00H
00H
00H
00H
00H
TL1
User’s Manual U19601EJ2V0UD
f
XX
UCnC
9CH
9CH
9CH
9CH
9CH
9CH
9CH
C0H
9CH
9CH
4EH
0CH
0AH
26H
13H
06H
05H
04H
TL2
= 48 MHz
ERR (%)
−4.00
−4.00
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.00
0.16
0.16
0.16
1.05
1.05
0.00
0.00
0.00
UCnC
07H
06H
05H
04H
03H
02H
01H
01H
00H
00H
00H
00H
00H
00H
00H
TL1
Setting prohibited
Setting prohibited
f
XX
UCnC
D0H
D0H
D0H
D0H
D0H
D0H
D0H
0DH
D0H
1AH
TL2
80H
68H
34H
08H
04H
= 32 MHz
ERR (%)
−1.54
−1.54
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.00
0.16
0.16
0.16
0.00
0.00
UCnC
TL1
07H
06H
05H
04H
03H
02H
01H
01H
00H
00H
00H
00H
00H
00H
00H
Setting prohibited
f
XX
UCnC
9CH
9CH
9CH
9CH
9CH
9CH
C0H
9CH
4EH
4EH
27H
13H
0AH
06H
05H
TL2
= 24 MHz
ERR (%)
−4.00
−4.00
−2.3
0.16
0.16
0.16
0.16
0.16
0.16
0.00
0.16
0.16
0.16
1.05
0.00