UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 852

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

850
CHAPTER 18 CLOCKED SERIAL INTERFACE E WITH FIFO (CSIE)
CEnRXE
• The CEnRXE bit is reset when the CEnPWR bit is cleared to 0.
• When the CEnPWR bit = 1, after the CEnRXE bit has been cleared to 0, setting
CEnTMS
• Specifies the transfer direction when data is written from the CEnTX0 register to
• The delay mode (CEnSIT bit = 1) is valid only in the master mode (when the
• If the CEnSIT bit is set to 1 in the continuous mode (TRMDn bit = 1), the INTCEnT
CEnDIR
CEnSIT
the CEnRXE bit to 1 before 2 cycles of the operation clock (f
The receive operation is enabled after the CEnRXE bit has been set to 1 and 2
cycles of the operation clock (f
the CSIBUFn register or read from the CEnRX0 and CSIBUFn registers.
CEnCKS2 to CEnCKS0 bits are other than 111). In the slave mode (when the
CEnCKS2 to CEnCKS0 bits are 111), do not set the delay mode. Even if the
delay mode is set, INTCEnT is not affected by the CEnSIT bit.
interrupt is not output except when the last data set by the CEnCTL3.CEnSFN3 to
CEnCTL3.CEnSFN0 bits is transferred, but a delay of half a clock (1/2 serial clock)
can be inserted between each data transfer.
0
1
0
1
0
1
0
1
Disables reception.
Enables reception.
Single mode
Continuous mode
MSB first
LSB first
No delay
Delay mode (In the continuous mode (TRMDn = 1), the next data transfer
is delayed half a cycle because a delay of half a cycle is inserted when
transfer of 1-bit data is complete.)
Controls delay of the transmission completion interrupt signal (INTCEnT)
User’s Manual U19601EJ2V0UD
Specifies the transfer direction (MSB/LSB)
XX
Enables or disables reception
Specifies the transfer mode
) have elapsed.
XX
) elapse is disabled.
(2/2)