UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 773

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) Reception interrupt request signal
(a) Reception end interrupt request signal (INTUBnTIR)
• In single mode (UBnFIC0.UBnMOD bit = 0)
• In FIFO mode (UBnFIC0.UBnMOD bit = 1)
When UBnCTL0.UBnRXE bit = 1 and the reception of one frame of data is ended (the stop bit is
detected) in the single mode, a reception end interrupt request signal (INTUBnTIR) is generated and
the receive data in the receive shift register is transferred to the UBnRX register at the same time.
Also, if an overrun error occurs, the receive data at that time is not transferred to the UBnRX register,
and a reception error interrupt request signal (INTUBnTIRE) is generated.
If a parity error or framing error occurs during the reception operation, the reception operation
continues up to the position at which the stop bit is received.
INTUBnTIRE signal occurs (the receive data in the receive shift register is transferred to the UBnRX
register).
If the UBnRXE bit is reset (0) during a receive operation, the receive operation is immediately stopped.
At this time, the contents of the UBnRX register remain unchanged, the contents of the UARTBn status
register (UBnSTR) are cleared, and the INTUBnTIR and INTUBnTIRE signals do not occur.
No INTUBnTIR signal is generated when the UBnRXE bit = 0 (reception is disabled).
In the FIFO mode, the reception end interrupt request signal (INTUBnTIR) occurs when data of one
frame has been received (stop bit is detected) and when as many receive data as the number specified
as the trigger by the UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits are transferred from the receive shift
register to receive FIFO. If an overflow error occurs, the receive data is not transferred to receive FIFO
and the reception error interrupt request signal (INTUBnTIRE) occurs.
If a parity error or framing error occurs during reception, reception continues up to the reception
position of the stop bit. After reception has been completed, the INTUBnTIRE signal occurs and the
receive data in the receive shift register is transferred to receive FIFO. At this time, error information is
appended as the UBnRXAP.UBnPEF or UBnRXAP.UBnFEF bit = 1. If the INTUBnTIRE signal occurs,
the error data can be recognized by reading receive FIFO as a 16-bit register, UBnRXAP.
Remark
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
n = 0, 1
User’s Manual U19601EJ2V0UD
After completion of reception, an
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