UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 648
UPD70F3785GJ-GAE-AX
Manufacturer Part Number
UPD70F3785GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3785GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3785GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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646
Write signal of
request signal
TAB1CMS bit
(4) Rewriting TAB1OPT0.TAB1CMS bit
<1> If the TAB1CCR1 register is rewritten when the TAB1CMS bit is 0, the transfer request signal is set.
<2> The register is not transferred because the TAB1CMS bit is set to 1 and the transfer request signal is
<3> The transfer request signal is not set even if the TAB1CCR1 register is written when the TAB1CMS bit is 1.
<4> The transfer request signal is not set even if the TAB1CCR1 register is written when the TAB1CMS bit is 1,
<5> The transfer request signal is set if the TAB1CCR1 register is written when the TAB1CMS bit is 0.
<6> Once transfer has been performed, the transfer request signal is cleared. Therefore, transfer is not
CCR1 buffer
TAB1CCR1
TAB1CCR1
Transfer
Transfer
The TAB1CMS bit can select the anytime rewrite mode and batch rewrite mode. This bit can be rewritten
during timer operation (when TAB1CTL0.TAB1CE bit = 1). However, the operation and caution illustrated in
Figure 11-36 are necessary.
If the TAB1CCR1 register is written when the TAB1CMS bit is cleared to 0, a transfer request signal (internal
signal) is set.
When the transfer request signal is set, the register is transferred at the next transfer timing, and the transfer
request signal is cleared. This transfer request signal is also cleared when the TAB1CMS bit is set to 1.
counter
register
register
If the TAB1CMS bit is set to 1 in this status, the transfer request signal is cleared.
cleared.
so even if the TAB1CMS bit is cleared to 0, transfer does not occur at the subsequent transfer timing.
Transfer is performed at the subsequent transfer timing and the transfer request signal is cleared.
performed at the next transfer timing.
timing
16-bit
0000H
i
CHAPTER 11 MOTOR CONTROL FUNCTION
Figure 11-36. Rewriting TAB1CMS Bit
i
User’s Manual U19601EJ2V0UD
Clear
<1>
<2>
k
<3>
<4>
r
r
Clear
<5>
s
s
<6>
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