UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 243
UPD70F3785GJ-GAE-AX
Manufacturer Part Number
UPD70F3785GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3785GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3785GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(4) TAAn I/O control register 1 (TAAnIOC1)
The TAAnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals
(TIAAn0, TIAAn1 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TAAnIOC1
(n = 0 to 5)
After reset: 00H
Cautions 1. Rewrite
TAAnIS3
TAAnIS1
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
0
0
1
1
0
0
1
1
7
0
TAAnIS2
TAAnIS0
2. The TAAnIS3 to TAAnIS0 bits are valid only in the free-
R/W
TAAnCTL0.TAAnCE bit = 0.
written when the TAAnCE bit = 1.)
mistakenly performed, clear the TAAnCE bit to 0 and then
set the bits again.
running timer mode and the pulse width measurement
mode.
performed.
6
0
0
1
0
1
0
1
0
1
Address:
User’s Manual U19601EJ2V0UD
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
Capture trigger input signal (TIAAn1 pin) valid edge setting
Capture trigger input signal (TIAAn0 pin) valid edge setting
In all other modes, a capture operation is not
5
0
the
TAAnIS3
TAA0IOC1 FFFFF633H, TAA1IOC1 FFFFF643H,
TAA2IOC1 FFFFF653H, TAA3IOC1 FFFFF663H,
TAA4IOC1 FFFFF673H, TAA5IOC1 FFFFF683H
4
0
TAAnIS3 TAAnIS2 TAAnIS1 TAAnIS0
to
3
TAAnIS0
(The same value can be
2
If rewriting was
bits
1
when
0
the
241
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