UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 760
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UPD70F3785GJ-GAE-AX
Manufacturer Part Number
UPD70F3785GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3785GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3785GJ-GAE-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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16.5 Interrupt Request Signals
request signal, reception end interrupt request signal, transmission enable interrupt request signal, FIFO transmission
end interrupt request signal, and reception timeout interrupt request signal.
758
The following five types of interrupt requests are generated from UARTBn.
The default priorities among these five types of interrupt requests is, from high to low, reception error interrupt
• Reception error interrupt request signal (INTUBnTIRE)
• Reception end interrupt request signal (INTUBnTIR)
• Transmission enable interrupt request signal (INTUBnTIT)
• FIFO transmission end interrupt request signal (INTUBnTIF)
• Reception timeout interrupt request signal (INTUBnTITO)
(1) Reception error interrupt request signal (INTUBnTIRE)
(a) Single mode
(b) FIFO mode
When reception is enabled, a reception error interrupt request signal is generated according to the logical
OR of the three types of reception errors (parity error, framing error, overrun error) explained for the
UBnSTR register.
When reception is disabled, no reception error interrupt request signal is generated.
When reception is enabled, a reception error interrupt request signal is generated according to the logical
OR of the three types of reception errors (parity error, framing error, overflow error) explained for the
UBnSTR register.
When reception is disabled, no reception error interrupt request signal is generated.
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
Table 16-4. Generated Interrupts and Default Priorities
Reception error
Reception end
Transmission enable
FIFO transmission end
Reception timeout
User’s Manual U19601EJ2V0UD
Interrupt
Priority
1
2
3
4
5
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