UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 280

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from
the TOAAn1 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and
restarted. (The output of the TOAAn0 pin is inverted. The TOAAn1 pin outputs a high level regardless of the status
(high/low) when a trigger occurs.)
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H at the same
time. The compare match interrupt request signal INTTAAnCC1 is generated when the count value of the 16-bit
counter matches the value of the CCR1 buffer register.
bit counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H.
used as the trigger.
278
16-bit timer/event counter AA waits for a trigger when the TAAnCE bit is set to 1. When the trigger is generated, the
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The compare match request signal INTTAAnCC0 is generated the next time the 16-bit counter counts after its
The value set to the TAAnCCRm register is transferred to the CCRm buffer register when the count value of the 16-
The valid edge of an external trigger input signal, or setting the software trigger (TAAnCTL1.TAAnEST bit) to 1 is
Remark
External trigger input
(only when software
INTTAAnCC0 signal
INTTAAnCC1 signal
TAAnCCR0 register
TAAnCCR1 register
TOAAn0 pin output
TOAAn1 pin output
(TIAAn0 pin input)
Active level width = (Set value of TAAnCCR1 register) × Count clock cycle
Cycle = (Set value of TAAnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TAAnCCR1 register)/(Set value of TAAnCCR0 register + 1)
trigger is used)
16-bit counter
TAAnCE bit
n = 0 to 5
m = 0, 1
FFFFH
0000H
Figure 7-22. Basic Timing in External Trigger Pulse Output Mode
trigger
Wait
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
for
Active level
width (D
Cycle (D
D
1
1
)
D
0
User’s Manual U19601EJ2V0UD
0
+ 1)
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
D
D
0
1
D
1
D
0
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)