UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 1495

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.5.6 Serial management interface
statuses, and for communicating with the PHY device when auto-negotiation is used.
the serial management interface.
MDIO
MDC
The Ethernet controller has a pair of serial management interfaces which can be used to set a PHY device, to read
Set the the address of the PHY device to be connected by Ethernet controller to the MADR register before using
(1) Overview of serial management interface
(a) MDC clock
(b) Serial management frame structure
The management data clock (MDC) is generated by dividing the Ethernet control clock (f
The division ratio is set by the MIIC.CLKS bits.
If MIIC.PHYSEL is set to 0 (default value), MDC is output only when a management frame is transmitted or
received.
MDC is always output when MIIC.PHYSEL = 1.
If communication with the PHY device has failed when MIIC.PHYSEL = 0, set MIIC.PHYSEL to 1.
The Ethernet controller generates the serial management frame shown below by writing a value to the
MCMD or MWTD register.
Bit 4
0
0
0
0
1
1
1
1
(Preamble)
PRE
Table 23-7. MIIC Register: CLKS Bits and f
Figure 23-12. Serial Management Frame Structure
MIIC.CLKS Bits
(Start bit)
ST
Bit 3
(Operation)
CHAPTER 23 ETHERNET CONTROLLER
0
0
1
1
0
0
1
1
OP
User’s Manual U19601EJ2V0UD
PHYAD
Bit 2
REGAD
0
1
0
1
0
1
0
1
(Turnaround)
TA
EC
Frequency
Frequency Range of f
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
33 MHz or less
50 MHz or less
(Data)
DATA
EC
EC
Input
).
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