UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 1518

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<1> Initializing the Ethernet controller
<2> Creating buffer descriptors for the transmission and reception data
<3> Setting the transmission buffer descriptor register and enabling transmission
<4> Reading the transmission data
<5> Transmitting packets
<6> Reporting the end of DMA transmission
<7> Preparing the next data
<8> Reporting the end-of-chain descriptor
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descriptors, set the bits of the transmission buffer descriptor as follows: Set the E bit (to 1 to indicate the end of
the packet data), set the T bit (to 0), set the U bit (to 0), and set the size bit.
Initialize the Ethernet controller using the procedure shown in 23.3 Initialization.
Create buffer descriptors for the transmission and reception data in the data-only RAM. When creating the
Read the transmission data from the memory using DMA.
If the E bit of the transmission buffer descriptor is 0, the next descriptor can be read.
Transmit the packet including the preamble, SFD, data, and FCS.
Report the end of transmission to the CPU by generating the TXI interrupt request.
Report the arrival of the end-of-chain descriptor to the CPU by generating the TECI interrupt request.
Set the transmission buffer descriptor address to the TXDP register. Then set the TXS (transmission enable) bit of
the ETHMODE register.
The CPU checks the transmission status and prepares the next data.
CHAPTER 23 ETHERNET CONTROLLER
User’s Manual U19601EJ2V0UD