UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 873

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(9) Single mode
The single mode is set when the CEnCTL0.CEnTMS bit is 0 (n = 0, 1).
In this mode, transfer is started when the CEnTXE bit or CEnRXE bit is set to 1 and when data is in the
CSIBUFn register (CEnSTR.CEnEMF bit = 0).
If no data is in the CSIBUFn register (CEnEMF bit = 1), transfer is kept waiting until transmit data or dummy
data is written to the CEnTX0 register.
When data is written to the CEnTX0 register while transmission or reception is enabled (CEnTXE or CEnRXE
bit is 1), the CEnSTR.CEnTSF bit (transfer status flag) is set to 1. If transfer is not in the wait status, the
transfer data indicated by the SIOn load CSIBUFn pointer is loaded from the CEnSTR.CEnTSF bit, and
transfer processing is started.
If the read operation (CEnRX0 register read) of the previously received data has been completed before one
data has been transferred in the reception mode or transmission/reception mode, the received data is stored
from the SIOn register to the CEnRX0 register, the transmission/reception completion interrupt (INTCEnT) is
output, and the SIOn load CSIBUFn pointer is incremented. If the read operation of the previously received
data has not been completed, the wait status is set and storing the receive data in the CEnRX0 register,
outputting the INTCEnT interrupt, and incrementing the SIOn load CSIBUFn pointer are held pending, until all
previously received data is read output from the CEnRX0 register.
In the transmission mode, the INTCEnT interrupt is output and the SIOn load pointer is incremented when
transfer processing of one data has been completed (the CEnRX0 register is always in the read complete
status because no data is stored from the SIOn register to the CEnRX0 register).
In all modes (transmission, reception, and transmission/reception modes), if the CSIBUFn register is empty
(write CSIBUFn pointer value = SIOn load CSIBUFn pointer value) when transfer processing of one data has
been completed, the CEnTSF bit is cleared to 0. The value of the “number of remaining data in the CSIBUFn
register (write CSIBUFn pointer – SIOn load pointer)” can always be read from the CEnSTR.CEnSFP3 to
CEnSTR.CEnSFP0 bits.
Caution Be sure to confirm that the CEnSTR.CEnFLF register is 0 when writing data to the CEnTX0
register. Even if data is written to this register when CEnFLF bit is 1, the CSIBUFn overflow
interrupt (INTCEnTIOF) is output, and the written data is ignored.
CHAPTER 18 CLOCKED SERIAL INTERFACE E WITH FIFO (CSIE)
User’s Manual U19601EJ2V0UD
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