UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 933

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

INTCFnT signal
(2) Operation timing
CFnTSF bit
SCKFn pin
SOFn pin
(1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write C3H to the CFnCTL0 register, and select the transmission mode, MSB first, and continuous
(4) The CFnSTR.CFnTSF bit is set to 1 by writing the transmit data to the CFnTX register, and the device
(5) When a serial clock is input, output the transmit data from the SOFn pin in synchronization with the
(6) When transfer of the transmit data from the CFnTX register to the shift register is completed and
(7) To continue transmission, write the transmit data to the CFnTX register again after the INTCFnT signal
(8) When a serial clock is input following completion of the transmission of the transfer data length set with
(9) When transfer of the transmit data from the CFnTX register to the shift register is completed and
(10) When the clock of the transfer data length set with the CFnCTL2 register is input without writing to the
(11) To release the transmission enable status, write CFnCTL0.CFnPWR bit = 0 and CFnCTL0.CFnTXE bit
Caution In continuous transmission mode, the reception completion interrupt request signal
Remark
external clock (SCKFn), and slave mode.
transfer mode at the same time as enabling the operation of the communication clock (f
waits for a serial clock input.
serial clock.
writing to the CFnTX register is enabled, the transmission enable interrupt request signal (INTCFnT) is
generated.
is generated.
the CFnCTL2 register, continuous transmission is started.
writing to the CFnTX register is enabled, the INTCFnT signal is generated.
transmission with the current transmission, do not write to the CFnTX register.
CFnTX register, clear the CFnTSF bit to 0 to end transmission.
= 0 after checking that the CFnTSF bit = 0.
(1)
(2)
(3)
(INTCFnR) is not generated.
n = 0 to 4 (V850ES/JH3-E)
n = 0 to 6 (V850ES/JJ3-E)
(4)
(5)
Bit 7
(6)
Bit 6
CHAPTER 19 CLOCKED SERIAL INTERFACE F (CSIF)
Bit 5
Bit 4 Bit 3
(7)
User’s Manual U19601EJ2V0UD
Bit 2
Bit 1
Bit 0
(8)
Bit 7
(9)
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
(10)
Bit 0
To end continuous
CCLK
(11)
).
CCLK
) =
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