UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 318

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

316
(c) Processing of overflow when two capture registers are used
Care must be exercised in processing the overflow flag when two capture registers are used. First, an
example of incorrect processing is shown below.
The following problem may occur when two pulse widths are measured in the free-running timer mode.
<1> Read the TAAnCCR0 register (setting of the default value of the TIAAn0 pin input).
<2> Read the TAAnCCR1 register (setting of the default value of the TIAAn1 pin input).
<3> Read the TAAnCCR0 register.
<4> Read the TAAnCCR1 register.
When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the
other capture register may not obtain the correct pulse width.
Use software when using two capture registers. An example of how to use software is shown below.
TAAnCCR0 register
TAAnCCR1 register
INTTAAnOV signal
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
Read the overflow flag. Because the flag is cleared in <3>, 0 is read.
Because the overflow flag is 0, the pulse width can be calculated by (D
TIAAn0 pin input
TIAAn1 pin input
16-bit counter
TAAnOVF bit
Example of incorrect processing when two capture registers are used
TAAnCE bit
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
D
00
User’s Manual U19601EJ2V0UD
<1>
D
10
<2>
D
00
D
D
01
10
<3>
D
11
<4>
11
D
− D
01
10
D
) (incorrect).
11
01
− D
00
).