UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 736

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

channels.
16.1 Features
734
In the V850ES/JH3-E and V850ES/JJ3-E, asynchronous serial interface B with FIFO (UARTBn) is provided with 2
• Transfer rate: Maximum 300 bps to 3.125 Mbps (using a dedicated baud rate generator)
• Full-duplex communications
• Single mode and FIFO mode selectable
• Two-pin configuration
• Reception error detection function
• Interrupt sources: 5 types
• The character length of transmit/receive data is specified according to the UBnCTL0 register
• Character length: 7 or 8 bits
• Parity functions: Odd, even, 0, or none
• Transmission stop bits: 1 or 2 bits
• MSB first/LSB first selectable for transfer data
• On-chip dedicated baud rate generator
Remark
• Single mode: 8-bit × 1-stage data register (UBnTX register or UBnRX register) is used for each of
• FIFO mode
TXDBn: Transmit data output pin
RXDBn: Receive data input pin
• Overflow error (FIFO mode only)
• Parity error
• Framing error
• Overrun error (single mode only)
• Reception error interrupt request signal (INTUBnTIRE)
• Reception end interrupt request signal (INTUBnTIR)
• Transmission enable interrupt request signal (INTUBnTIT)
• FIFO transmission end interrupt request signal (INTUBnTIF) (FIFO mode only)
• Reception timeout interrupt request signal (INTUBnTITO) (FIFO mode only)
Transmit FIFO: UBnTX register (8 bits × 16 stages).
Receive FIFO: UBnRXAP register (16 bits × 16 stages)
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
n = 0, 1
transmission and reception.
The higher 8 bits of the UBnRXAP register store information about errors in the received
data.
User’s Manual U19601EJ2V0UD