UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 766
UPD70F3785GJ-GAE-AX
Manufacturer Part Number
UPD70F3785GJ-GAE-AX
Description
MCU 32BIT V850ES/JX3-E 144-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Er
Datasheet
1.UPD70F3778GF-GAT-AX.pdf
(1817 pages)
Specifications of UPD70F3785GJ-GAE-AX
Core Processor
RISC
Core Size
32-Bit
Speed
50MHz
Connectivity
CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
100
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
124K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number:
UPD70F3785GJ-GAE-AX
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Renesas Electronics America
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(ii) During reception (reading from receive FIFO)
• Each time the data of 1 byte is transferred to receive FIFO from the receive shift register, a
• In the pointer mode, be sure to fix the UBnFIC2.UBnRT3 to UBnFIC2.UBnRT0 bits to 0000 (set
• Reading receive data from receive FIFO by DMA is prohibited. The operation is not guaranteed if
• After the reception end interrupt request signal (INTUBnTIR) has been acknowledged, data of the
reception end interrupt request signal (INTUBnTIR) occurs.
number of receive data: 1 byte) as the number of receive data set as the trigger for receive FIFO
when the reception end interrupt request signal (INTUBnTIR) occurs. If any other setting is made,
the operation is not guaranteed.
DMA control is used.
number of bytes stored in receive FIFO can be read from receive FIFO by referencing the
UBnFIS0 register. In some cases, however, data is not stored in receive FIFO even though the
INTUBnTIR signal is generated (UBnFIS0.UBnRB4 to UBnFIS0.UBnRB0 bits = 00000). In these
cases, do not read data from receive FIFO. Always read data from receive FIFO when the number
of bytes stored in receive FIFO is 1 byte or more (UBnRB4 to UBnRB0 bits = other than 00000).
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE B WITH FIFO (UARTBn)
User’s Manual U19601EJ2V0UD
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