UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 12

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 196
CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 219
10
4.4
4.5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.1
6.2
6.3
6.4
6.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.12
Port Register Settings When Alternate Function Is Used...................................................177
Cautions ...................................................................................................................................191
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
Features ...................................................................................................................................196
Bus Control Pins .....................................................................................................................197
5.2.1
5.2.2
Memory Block Function .........................................................................................................199
Bus Access ..............................................................................................................................200
5.4.1
5.4.2
5.4.3
Wait Function...........................................................................................................................208
5.5.1
5.5.2
5.5.3
5.5.4
Idle State Insertion Function..................................................................................................212
Bus Hold Function ..................................................................................................................213
5.7.1
5.7.2
5.7.3
Bus Priority ..............................................................................................................................215
Bus Timing...............................................................................................................................216
Overview ..................................................................................................................................219
Configuration...........................................................................................................................220
Registers ..................................................................................................................................222
Operation .................................................................................................................................227
6.4.1
6.4.2
PLL Function ...........................................................................................................................228
6.5.1
Port 7.........................................................................................................................................148
Port 9.........................................................................................................................................151
Port CM .....................................................................................................................................160
Port CS......................................................................................................................................163
Port CT ......................................................................................................................................166
Port DH......................................................................................................................................168
Port DL ......................................................................................................................................175
Cautions on setting port pins .....................................................................................................191
Cautions on bit manipulation instruction for port n register (Pn) ................................................194
Cautions on on-chip debug pins (V850ES/JH3-E only) .............................................................195
Cautions on P54/INTP11/DRST pin ..........................................................................................195
Cautions on P51 pin when power is turned on ..........................................................................195
Hysteresis characteristics ..........................................................................................................195
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed.................198
Pin status in each operation mode ............................................................................................198
Number of clocks for access......................................................................................................200
Bus size setting function ............................................................................................................200
Access by bus size ....................................................................................................................201
Programmable wait function ......................................................................................................208
External wait function ................................................................................................................209
Relationship between programmable wait and external wait .....................................................210
Programmable address wait function.........................................................................................211
Functional outline ......................................................................................................................213
Bus hold procedure ...................................................................................................................214
Operation in power save mode..................................................................................................214
Operation of each clock .............................................................................................................227
Clock output function .................................................................................................................227
Overview ...................................................................................................................................228
User’s Manual U19601EJ2V0UD