UPD70F3785GJ-GAE-AX Renesas Electronics America, UPD70F3785GJ-GAE-AX Datasheet - Page 1484

• Manufacturer Part Number: UPD70F3785GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3-E 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Er

Specifications of UPD70F3785GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CSI, EBI/EMI, Ethernet, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 124K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1482
(5) Inter-packet gap (IPG)
The IPG is specified by the IPGT register if the source terminal successively transmits data; otherwise, it is be
specified by the IPGR register.
The Ethernet controller starts counting the IPG when the source or an other terminal has completed
transmission. If a request for next transmission is issued from the FIFO after transmission from the source
terminal is executed and before the IPG count reaches the value of the IPGT register, it is assumed that the
data is to be transmitted successively (back to back), and transmission is started as soon as counting is
complete.
When a packet is to be transmitted after transmission from an other terminal, the IPG count is controlled by the
IPGR register. The IPGR register specifies the total time of the IPG in its IPGR2 field. The time during which a
carrier is to be detected in the first half of the IPG is set in the IPGR1 field. If a carrier is detected during the
time set in the IPGR1 field, the Ethernet controller waits for the end of the carrier and then starts IPG counting
from the beginning. If no carrier is detected during the time set in the IPGR1 field, transmission is started after
the IPG period set in the IPGR2 field has elapsed.
If transmission is not started before the time required to transmit 24,288 bits has elapsed (2.43 ms when the
data rate is 10 Mbps and 243.88
transmission request has been received from the FIFO, an excessive transmission delay is assumed,
transmission is aborted, and the transmit data is discarded.
The set value of the IPGT and IPGR registers and the actual IPG period are calculated by the following
expression.
[When the data rate is 100 Mbps]
Back-to-back transmission:
Non back-to-back transmission: IPG = (5 + IPGR2) x 40 ns (default value: 960 ns)
Carrier sense time:
[When the data rate is 10 Mbps]
Back-to-back transmission:
Non back-to-back transmission: IPG = (5 + IPGR2) x 400 ns (default value: 9.6
Carrier sense time:
Caution Because of the specification of IEEE802.3, set the IPG to 960 ns or more when the data rate is
Transmit packet
100 Mbps and 9.6
The default value of the IPGT and IPGR registers is the minimum rated value and may be
used as is.
Frame data
Figure 23-6. IPG During Back-To-Back Transmission
μ
s or more when the data rate is 10 Mbps.
CHAPTER 23 ETHERNET CONTROLLER
Minimum gap = IPGT
IPG = (5 + IPGT) x 40 ns (default value: 960 ns)
(2 + IPGR1) x 40 ns (default value: 640 ns)
IPG = (5 + IPGT) x 400 ns (default value: 9.6
(2 + IPGR1) x 400 ns (default value: 6.4
μ
s when the data rate is 100 Mbps to have occurred) after the next
User’s Manual U19601EJ2V0UD
IPG
Preamble
Transmit packet
SFD
μ
s)
μ
s)
μ
s)
Frame data
Time