TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 128

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

7.6
Exception / Interrupt-Related Registers
31-29
28-24
23-21
20-16
15-13
12-8
7-5
4-0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
7.6.2.24
Bit
PRI_7
−
PRI_6
−
PRI_5
−
PRI_4
−
0xE000_ED1C
0xE000_ED18
0xE000_ED20
Bit Symbol
tion.
bits for assigning a priority.
Bus Fault and Usage Fault. Unused bits return "0" when read, and writing to unused bits has no effect.
Each exception is provided with eight bits of a System Handler Priority Register.
The following shows the addresses of the System Handler Priority Registers corresponding to each excep-
The number of bits to be used for assigning a priority varies with each product. This product uses three
The following shows the fields of the System Handler Priority Registers for Memory Management,
System Handler Priority Register
31
23
15
0
0
0
7
0
R/W
R
R/W
R
R/W
R
R/W
R
Type
31
PRI_7
PRI_6
PRI_5
PRI_4
30
22
14
0
0
0
6
0
Reserved
Read as 0,
Priority of Usage Fault
Read as 0,
Priority of Bus Fault
Read as 0,
Priority of Memory Management
Read as 0,
(SysTick)
(SVCall)
PRI_11
PRI_15
PRI_7
24 23
29
21
13
0
0
0
5
0
(Usage Fault)
(PendSV)
Page 104
PRI_10
PRI_14
PRI_6
28
20
12
0
0
0
4
0
-
-
-
-
16 15
27
19
11
Function
0
0
0
3
0
-
-
-
-
(Bus Fault)
PRI_13
PRI_5
PRI_9
26
18
10
0
0
0
2
0
-
-
-
-
8 7
(Memory Management)
(Debug Monitor)
25
17
PRI_12
0
0
9
0
1
0
-
-
-
-
PRI_4
PRI_8
TMPM362F10FG
0
24
16
0
0
8
0
0
0
-
-
-
-