TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 322

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

9.5
Special Functions
9.5
9.5.1
Special Functions
ta, and the address changes dramatically depending on the special rule. Since DMA can transfer data only by
using consecutive addresses, it is necessary to make required settings at locations where addresses changes.
dress, number of transfers, and transfer bus width) by re-loading them each time a specified number of DMA
executions have completed via a pre-set "Linked List" where the CPU does not need to control the operation.
the DMACCxControl register.
Control<I>=0 and DMACCxConfiguration<ITC>=1 to start transfers. Then in the last DMA transfer setting
flow, if <I>=1 is set, the transfer end interrupt occurs only in the last transfer. If this bit is cleared, branch pro-
cedure added conditions can be set even if LLI is used for transfers. To clear the interrupt, the corresponding
bit of DMACIntTCClear register should be controlled.
Scatter/gather function
When removing a part of image data and transferring it, image data cannot be handled as consecutive da-
The scatter/gather function can consecutively operate DMA settings (transfer source address, destination ad-
Setting "1" in the DMACCxLLI register enables/disables the operation.
The items that can be set with Linked List are configured with the following 4 words:
It is also possible to generate interrups in conjunction with the scatter/gather function.
If DMACCxControl<I>=1 and DMACCxConfiguration<ITC>=1 are set, DMA transfer end interrupt occurs.
An interrupt can be generated after each LLI operation by setting the terminal count interrupt enable bit of
In scatter/gather function, if DMA transfer end interrupt is set to occur only in the last transfer, set DMACCx-
Screen image
1. DMACCxSrcAddr
2. DMACCxDestAddr
3. DMACCxLLI
4. DMACCxControl
Transfer only a part
of the screen image
Page 298
Screen Data
Addresses are not
contiguous
TMPM362F10FG