TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 703

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

23. ROM protection
23.1
23.2
23.2.1
23.2.2
The TMPM362F10FG offers two kinds of ROM protection/ security functions.
One is a write/ erase-protection function for the internal flash ROM data.
The other is a security function that restricts internal flash ROM data readout and debugging.
Outline
Future
for each block.
cels the protection.
"Flash" for programming details.
The write/ erase-protection function enables the internal flash to prohibit the writing and erasing operation
To activate the function, write "1" to the corresponding bits to a block to protect. Writing "0" to the bits can-
The protection settings of the bits can be monitored by the FCFLCS <BLPRO[9:0]> bit. See the chapter
The security function restricts flash ROM data readout and debugging.
This function is available under the conditions shown below.
Table 23-1 shows details of the restrictions by the security function.
Write/ erase-protection function
Security function
Note:The FCSECBIT <SECBIT> bit is set to "1" at a power-on reset right after power-on.
Table 23-1 Restrictions by the security function
1. The FCSECBIT <SECBIT> bit is set to"1".
2. All the protection bits (the FCFLCS<BLPRO> bits) used for the write/erase-protection function are
1) ROM data readout
2) Debug port
3) Command for flash memory
set to "1".
Item
Data can be read from CPU.
Communication of JTAG/SW and trace are prohibited
Writing a command to the flash memory is prohibited.
An attempt to erase the contents in the bits used for the write/
erase-protection erases all the protection bits.
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Details
TMPM362F10FG