TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 727

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

25.6.5
SPCLK period (Master)
SPCLK period (Slave)
SPCLK rise up time
SPCLK fall down time
Master mode : SPCLK low-level pulse width
Master mode : SPCLK high-level pulse width
Slave mode : SPCLK low-level pulse width
Slave mode : SPCLK high-level pulse width
Master mode :
SPCLK rise / fall → output valid
Master mode :
SPCLK rise / fall → output data hold
Master mode :
SPCLK rise / fall → input data valid delay time
Master mode :
SPCLK rise / fall → input data hold
Master mode :
SPFSS valid → SPCLK rise / fall
Slave mode :
SPCLK rise / fall → output data valid delay time
Slave mode :
SPCLK rise / fall → output data hold
Slave mode :
SPCLK rise / fall → input data valid delay time
Slave mode :
SPCLK rise / fall → input data hold
Slave mode :
SPFSS valid → SPCLK rise / fall
"T" is 1/2 cycles of an internal bus frequency (fsys) in the Equation of the table.
AC measurement condition
SSP Controller (SSP)
Note:The "Equation" column in the table shows the specifications under the conditions DVDD3 2.7
Note:Baud rate clock is set under below condition
・ Output level : High = 0.8 x DVDD3, Low = 0.2 x DVDD3
・ Input level : Refer low-level input voltage and high-level input voltage in DC Electrical Characteris-
・ Load capacitance : CL = 30pF
tics.
to 3.6 V.
Parameter
Page 703
Symbol
t
t
t
t
t
t
t
t
t
t
ODHM
t
t
t
t
ODSM
OFSM
ODSS
ODHS
OFSS
WHM
IDSM
IDHM
IDHS
WLM
WLS
WHS
IDSS
T
T
t
t
m
r
f
s
However more than
(m)T / 2 − 10.0
(m)T / 2 − 10.0
(m)T / 2 − 10.0
(n)T / 2 − 10.0
(n)T / 2 − 10.0
(n)T / 2 + (2T)
(m)T − 10.0
(3T) + 10.0
(n)T − 15.0
50 ns
(m)T
15.0
5.00
0.00
(n)T
Min
−
−
−
−
Equation
(m)T + 10.0
(3T) + 22.0
Max
10.0
10.0
15.0
−
−
−
−
−
−
−
−
−
−
−
−
−
52.5 − 72.5
(16MHz)
64 MHz
(8MHz)
n = 12
fsys =
m = 4
TMPM362F10FG
187.5
172.5
62.5
10.0
10.0
21.3
21.3
83.8
83.8
15.0
21.3
15.0
5.00
68.9
0.00
56.9
125
Unit
ns