TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 426

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

12.12
Transmission
12.12.3
12.12.3.1
12.12.3.2
Figure 12-7 Operation of Transmission Buffer (Double buffer is enabled)
rupt INTTXx is generated upon completion of data transmission.
mit buffer is moved to the transmit shift register. The INTTXx interrupt is generated at the same time
and the transmit buffer empty flag (SCxMOD2<TBEMP>) is set to "1". This flag indicates that the next
transmit data can be written. When the next data is written to the transmit buffer, the <TBEMP> flag is
cleared to "0".
Once transmission is enabled, data is transferred to the transmit shift register from the transmit buffer and
start transmission. If data exists in the FIFO, the data is moved to the transmit buffer immediately, and
the <TBEMP> flag is cleared to "0".
shown as below.
transmit buffer or FIFO, and setting the SCxMOD1<TXE> bit to "1". When the last transmit data is
moved to the transmit buffer, the transmit FIFO interrupt is generated. When transmission of the last data
is completed, the clock is stopped and the transmission sequence is terminated.
TX interrupt (INTTXx)
Transmit Operation
SCxMOD2<TBEMP>
If double buffering is disabled, the CPU writes data only to Transmit shift Buffer and the transmit inter-
If double buffering is enabled (including the case the transmit FIFO is enabled), data written to the trans-
When FIFO is enabled, the maximum 5-byte data can be stored using the transmit buffer and FIFO.
Settings and operations to transmit 4-byte data stream by setting the transfer mode to half duplex are
After above settings are configured, data transmission can be initiated by writing 5 bytes of data to the
Transmit shift register
Note:To use TX FIFO buffer, TX FIFO must be cleared after setting the SIO transfer mode (half du-
Operation of Transmission Buffer
Transmit FIFO Operation
SCxMOD1[6:5] =10
SCxFCNF[4:0] = 11011
SCxTFC[1:0] = 00
SCxTFC[7:6] = 11
SCxFCNF[0] = 1
Write data
plex/ full duplex) and enabling FIFO (SCxFCNF<CNFG>="1").
Transmit buffer
:Transfer mode is set to half duplex.
:Transmission is automatically disabled if FIFO becomes empty.
:The number of bytes to be used in the receive FIFO is the same as the interrupt
:generation fill level.
:Sets the interrupt generation fill level to "0".
:Clears receive FIFO and sets the condition of interrupt generation.
:Enable FIFO
DATA 1
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DATA 1
DATA 2
TMPM362F10FG