TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 542

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

15.4
Operations
15.4.3.2
mit Buffer Register (CECTBUF) are required.
(1)
(2)
(3)
Before transmitting data, transmission settings to the Transmit Control Register (CECTCR) and the Trans-
Preconfiguration
Start bit
1 to 16 bit cycles.
the signal stays high for the specified number of bit cycles, transmission starts.
"0" response during an ACK cycle results in an error.If not, logical "1" response during an ACK cy-
cle results in an error.
<CECSTRS> <CECSPRD> <CECDTRS> <CECDPRD> bits, the timing can be specified between
the defined fastest rising/cycle timing and the reference value.
bit, logical "0" and logical "1".
Specify the bus free wait time in the CECTCR<CECFREE> bits. It can be specified in a range of
Counting of the bus free wait time begins one bit cycle after the falling edge of the final bit. If
Set the CECTCR <CECBRD> bit when transmitting a broadcast message.If this bit is set, logical
Both start bit and data bit are capable of adjusting the rising timing and cycle. With the CECTCR
The following figures show how the waveforms differ according to the configurations of the start
Note:Use <CECDTRS> in the same settings used for CECRCR1<CECLNC>.
Bus Free Wait Time
Adjusting Transmission Waveform
Transmitting Broadcast Message
1bit cycle
Bus free wait time
Page 518
<CECSTRS>
121/fs - 7/fs to 121/fs
(approx.3.693 ms)
Beginning of transmission
<CECSPRD>
147/fs - 7/fs to 147/fs
(approx.4.486 ms)
TMPM362F10FG