TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 417

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

12.8
12.8.1
12.8.2
12.8.3
RXD
Transmit / Receive Buffer and FIFO
ing on the mode.
SCxMOD2<WBUF>.
mode or the UART mode is selected, it’s double buffered despite the <WBUF> settings. In other modes, it’s
according to the <WBUF> settings.
to "1". The FIFO buffer configuration is specified by SCxMOD1<FDPX[1:0]>.
Figure 12-3 shows the configuration of transmit buffer, receive buffer and FIFO.
Appropriate settings are required for using buffer and FIFO. The configuration may be predefined depend-
Transmit buffer and receive buffer are double-buffered. The buffer configuration is specified by
In the case of using a receive buffer, if SCLK input is set to generate clock output in the I/O interface
Table 12-11 shows correlation between modes and buffers.
In addition to the double buffer function above described, 4-byte FIFO can be used.
To enable FIFO, enable the double buffer by setting SCxMOD2<WBUF> to "1" and SCxFCNF<CNFG>
Configuration
Transmit / Receive Buffer
FIFO
Receive FIFO First stage
Figure 12-3 The Configuration of Buffer and FIFO
Receive shift register
Table 12-11 Mode and buffer Composition
Receive buffer
(SCLK output)
(SCLK input)
I/O interface
I/O interface
UART
Second stage
Third stage
Fourth stage
Mode
Transmit
Transmit
Transmit
Page 393
Receive
Receive
Receive
Double
Double
Single
Single
Single
Single
Transmit FIFO
"0"
SCxMOD2<WBUF>
Transmit shift register
Transmit buffer
Double
Double
Double
Double
Double
Double
First stage
Second stage
Third stage
Fourth stage
"1"
TMPM362F10FG
TXD