TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 144

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

7.6
Exception / Interrupt-Related Registers
31-5
4
3
2
1
0
After pin reset
After pin reset
After pin reset
After pin reset
7.6.3.9
Bit
bit symbol
bit symbol
bit symbol
bit symbol
Note 1: This flag indicates a reset generated by the SYSRESETREQ bit of the Application Interrupt and Reset Control Regis-
Note 2: This product has power-on reset circuit and this register is initialized only by power-on reset. Therefore, "1" is set to
−
SYSRSTF
BUPRSTF
WDTRSTF
PINRSTF
PONRSTF
Bit Symbol
ter of the CPU's NVIC.
the <PONRSTF> bit in initial reset state right after power-on. Note that this bit is not set by the second and subse-
quent resets and this register is not cleared automatically. Write "0" to clear the register.
CGRSTFLG (Reset Flag Register)
31
23
15
0
0
0
7
0
-
-
-
-
R
R/W
R/W
R/W
R/W
R/W
Type
Read as 0,
Debug reset flag (Note1)
0: "0" is written
1: Reset from SYSRESETREQ
BACKUP reset flag
0: "0" is written
1: Reset from BACKUP mode release
WDT reset flag
0: "0" is written
1: Reset from WDT
RESET pin flag
0: "0" is written
1: Reset from RESET pin
Power-on flag
0: "0" is written
1: Reset from power-on reset
30
22
14
0
0
0
6
0
-
-
-
-
29
21
13
0
0
0
5
0
-
-
-
-
Page 120
SYSRSTF
28
20
12
0
0
0
4
0
-
-
-
BUPRSTF
Function
27
19
11
0
0
0
3
0
-
-
-
WDTRSTF
26
18
10
0
0
0
2
0
-
-
-
PINRSTF
25
17
0
0
9
0
1
1
-
-
-
TMPM362F10FG
PONRSTF
24
16
0
0
8
0
0
1
-
-
-