TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 419

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

12.10.2
12.10.3
from the parity received.
abled.
the transmit shift register with no data in the transmit buffer.
stops.
around the center. Regardless of the stop bit length settings in the SCxMOD2<SBLEN>register, the stop bit sta-
tus is determined by only 1.
This flag indicates a parity error in the UART mode and an under-run error in the I/O interface mode.
In the UART mode, <PERR> is set to "1" when the parity generated from the received data is different
In the I/O interface mode, <PERR> is set to "1" under the following conditions when a double buffer is en-
In the SCLK input mode, <PERR> is set to "1" when the SCLK is input after completing data output of
In the SCLK output mode, <PERR> is set to "1" after completing output of all data and the SCLK output
A framing error is generated if the corresponding stop bit is determined to be "0" by sampling the bit at
This bit is fixed to "0" in the I/O interface mode.
Note:To switch the I/O interface SCLK output mode to other modes, read the SCxCR register and
Note:To switch the I/O interface SCLK output mode to other modes, read the SCxCR register and
PERR Flag
FERR Flag
clear the overrun flag.
clear the underrun flag.
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TMPM362F10FG