TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 644

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

21.5
Alarm function
21.5
21.5.1
ing three signals is output to the ALARM pin.
rupt request simultaneously.
rupt Mode Control Register
By writing "1" to RTCPAGER<PAGE>, the alarm function of the PAGE1 registers is enabled. One of the follow-
In any cases shown above, the INTRTC outputs one cycle pulse of low-speed clock. It outputs the INTRTC inter-
The INTRTC interrupt signal is falling edge triggered. Specify the falling edge as the active state in the CG Inter-
Alarm function
1. "Low" pulse (when the alarm register corresponds with the clock)
2. 1Hz cycle "Low" pulse
3. 16Hz cycle "Low" pulse
alarm register correspond. The INTRTC interrupt is generated and the alarm is triggered.
NA> bit.
day 5th.
quency oscillation, a maximum of one clock delay at fs (about 30μs) may occur for the time register setting
to become valid.
"Low" pulse is output to the ALARM pin when the values of the PAGE0 clock register and the PAGE1
The alarm settings
Initialize the alarm with alarm prohibited. Write "1" to RTCRESTR<RSTALM>.
It makes the alarm setting to be 00 minute, 00 hour, 01 day and Sunday.
Setting alarm for min., hour, date and day is done by writing data to the relevant PAGE1 register.
Enable the alarm with the RTCPAGER <ENAALM> bit. Enable the interrupt with the RTCPAGER <INTE-
The following is an example program for outputting an alarm from the ALARM pin at noon (12:00) on Mon-
The above alarm works in synchronization with the low-speed clock. When the CPU is operating at high fre-
"Low" pulse (when the alarm register corresponds with the clock)
Note:To make the alarm work repeatedly (e.g. every Wednesday at 12:00), next alarm must be set during
RTCPAGER
RTCRESTR
RTCDAYR
RTCDATER
RTCHOURR
RTCMINR
RTCPAGER
RTCPAGER
the INTRTC interrupt routine that is generated when the time set for the alarm matches the RTC count.
←
←
←
←
←
←
←
←
7
0
1
0
0
0
0
0
1
6
0
1
0
0
0
0
0
0
5
0
0
0
0
0
0
0
0
4
0
1
0
0
1
0
0
0
3
1
0
0
0
0
0
1
1
Page 620
2
0
0
0
1
0
0
1
1
1
0
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
Disables alarm,sets PAGE1
Initializes alarm
Monday
5th day
Sets 12 o’clock
Sets 00 min
Enables alarm
Enables interrupts
TMPM362F10FG