TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 486

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

14.5
Control in the I2C Bus Mode
SCL (Line)
Internal SDA output (masterA)
Internal SDA output(master B)
SDA Line
"Low" level and Master B outputs the "High" level.
When the SCL line goes high at the point b, the slave device reads the SDA line data, i.e., data transmitted
by Master A. At this time, data transmitted by Master B becomes invalid.
fect the data transfer initiated by another master. If two or more masters have transmitted exactly the same
first data word, the arbitration procedure continues with the second data word.
If there is a difference between these two values, Arbitration Lost occurs and SBIxSR<AL> is set to "1".
ceiver.Therefore, the serial bus interface circuit stops the clock output during data transfer after <AL> is set
to "1".
Up until the point a, Master A and Master B output the same data. At the point a, Master A outputs the
Then Master A pulls the SDA bus line to the "Low" level because the line has the wired-AND connection.
This condition of Master B is called "Arbitration Lost". Master B releases its SDA pin, so that it does not af-
A master compares the SDA bus line level and the internal SDA output level at the rising of the SCL line.
When <AL> is set to "1", SBIxSR<MST, TRX> are cleared to "0", causing the SBI to operate as a slave re-
<AL> is cleared to "0" when data is written to or read from SBIxDBR or data is written to SBIxCR2.
Figure 14-7 Lost Arbitration
Page 462
a
b
Loses arbitration and sets the
internal SDA output to “1”.
TMPM362F10FG