TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 469

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

er, the SPFSS line is continuously asserted (held Low) and transmission of data occurs back to back.
frame. Each of the received values is transferred from the receive shifter on the falling edge of SPCLK, after
the LSB of the frame has been latched into the SSP.
Note 1: When transmission is disabled, SPDO terminal doesn't output and is high impedance status. This terminal
Note 2: SPDI terminal is always input and internal gate is open. In case of transmission signal will be high impedance sta-
For continuous transfers, data transmission begins and ends in the same manner as a single transfer. Howev-
The control byte of the next frame follows directly after the LSB of the received data from the current
Note:The off-chip slave device can tristate the receive line either on the falling edge of SPCLK after the
Note:[Example of connection] The SSP does not support dynamic switching between the master and
SPCLK
SPFSS
SPDO
SPDI
LSB has been latched by the receive shifter, or when the SPFSS pin goes "High".
needs to add suitable pull-up/down resistance to fix the voltage level.
tus, this terminal needs to add suitable pull-up/down resistance to fix the voltage level.
slave in the system. Each sample SSP is configured and connected as either a master or slave.
Figure 13-7 Microwire frame format (continuous transfer)
Hi-Z(Note2
LSB
Hi-Z(Note1
MSB
4 to 16bit
Page 445
LSB
MSB
Hi-Z(Note2
8bit
LSB
Hi-Z(Note1
MSB
TMPM362F10FG