TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 651
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TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
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- Download datasheet (8Mb)
22.2.1
22.2.2
nal oscillator has been stabilized, and that the RESET input is held at "0" for a minimum duration of 12 sys-
tem clocks (0.19μs with 64MHz operation; the "1/1" clock gear mode is applied after reset).
fer buses for flash memory program code on the old application and for serial I/O are different. It operates at
the single chip mode; therefore, a switch from normal mode in which user application is activated at the sin-
gle chip mode to User Boot Mode for programming flash is required. Specifically, add a mode judgment rou-
tine to a reset program in the user application.
with the user’s system setup condition. Also, flash memory programming routine that the user uniquely
makes up needs to be set in the new application. This routine is used for programming after being switched
to User Boot Mode. The execution of the programming routine must take place while it is stored in the area oth-
er than the flash memory since the data in the internal flash memory cannot be read out during delete / writ-
ing mode. Once re-programming is complete, it is recommended to protect relevant flash blocks from acciden-
tal corruption during subsequent Single-Chip (Normal mode) operations. Be sure not to cause any exceptions
including a non-maskable while User Boot Mode.
ternal memory. For a detailed description of the erase and program sequence, refer to "22.3 On-board Program-
ming of Flash Memory (Rewrite/Erase)".
Note 1: It is necessary to apply "0" to the RESET inputs upon power on for a minimum duration of 700
Note 2: While flash auto programming or erasing is in progress, at least 0.5 μs of reset period is re-
To reset the device, ensure that the power supply voltage is within the operating voltage range, that the inter-
User Boot mode is to use flash memory programming routine defined by users. It is used when the data trans-
The condition to switch the modes needs to be set by using the I/O of TMPM362F10FG in conformity
(1-A) and (1-B) are the examples of programming with routines in the internal flash memory and in the ex-
Reset Operation
User Boot Mode (Single chip mode)
μs regardless of the operating frequency.
quired regardless of the system clock frequency. In this condition, it takes approx. 2 ms to ena-
ble reading after reset.
Page 627
TMPM362F10FG
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