TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 571

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

17. Watchdog Timer(WDT)
17.1
Internal reset
bances and remedying them to return the CPU to normal operation.
dog timer pin (WDTOUT) by outputting "Low".
The watchdog timer (WDT) is for detecting malfunctions (runaways) of the CPU caused by noises or other distur-
If the watchdog timer detects a runaway, it generates a INTWDT interrupt or reset.
Also, the watchdog timer notifies of the detecting malfunction to the external peripheral devices from the watch-
Figure 17-1shows the block diagram of the watchdog timer.
Note:INTWDT interrupt is a factor of the non-maskable interrupts (NMI).
Configuration
fsys
WDMOD
Figure 17-1 Block Diagram of the Watchdog Timer
Binary counter
Control Register WDCR
Watchdog timer out
Selector
Watch dog timer
“0x4E”
Internal data bus
Write
Reset
control
“0xB1”
Page 547
Write
R
WDMOD<WDTE>
WDMOD<RESCR>
Q
S
TMPM362F10FG
Watchdog timer
interrupt
INTWDT
To internal reset
WDTOUT
RESET pin