TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 626

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

20.4
Description of Operations
20.4.5.5
20.4.5.6
MOD3<ADRST>) must be performed before starting AD conversion. The H/W activation method must
not be used to reactivate normal AD conversion.
(1)
To reactivate normal AD conversion while the conversion is underway, a software reset (AD-
Reactivating normal AD conversion
Conversion completion
generated. The result of AD conversion is stored in the storage register is the storage register, and
two registers change: the register ADMOD0<EOCFN> which indicates the completion of AD conver-
sion and the register ADMOD0<ADBFN>.Interrupt request, conversion register storage register and
<EOCFN><ADBFN> change with a different timing according to a mode selected.
version result registers (ADREG08 through ADRG7F) corresponding to a channel.
registers ADREG08 through ADREG7F. However, if interrupt setting on <ITM> is set to be gener-
ated each time one AD conversion is completed, the conversion result is stored only in ADREG08.
If interrupt setting on <ITM> is set to be generated each time four AD conversions are completed,
the conversion results are sequentially stored in ADREG08H through ADREG3B.If interrupt setting
on <ITM> is set to be generated each time eight AD conversions are completed, the conversion re-
sults are sequentially stored in ADREG08H through ADREG7F.
When normal AD conversion is completed, the AD conversion completion interrupt (INTAD) is
In mode other than fixed-channel repeat conversion mode, conversion results are stored in AD con-
In fixed-channel repeat conversion mode, the conversion results are sequentially stored in storage
Interrupt requests, flag changes and conversion result registers in each mode are as shown below.
Normal AD conversion completion
・ Fixed-channel single conversion mode
・ Channel scan single conversion mode
・ Fixed-channel repeat conversion mode
MOD0<ADBFN> is cleared to "0", and the interrupt request is generated.
MOD0<ADBFN> is set to "0", and the interrupt request INTAD is generated.
interrupt request INTAD is generated can be selected by setting ADMOD0<ITM> to an ap-
propriate setting. ADMOD0<EOCFN> is set with the same timing as this interrupt INTAD
is generated.
a. One conversion
b. Four conversions
After AD conversion completed, ADMOD0<EOCFN> is set to "1", AD-
Conversion results are stored a conversion result register correspond to a channel.
After the channel scan conversion is completed, ADMOD0<EOCFN> is set to "1", AD-
Conversion results are stored a conversion result register correspond to a channel.
ADMOD0<ADBFN> is not cleared to "0". It remains at "1". The timing with which the
version is completed. In this case, the conversion results are always stored in the stor-
age register ADREG08. After the conversion result is stored, <EOCFN> changes to
"1".
With <ITM[1:0]> set to "00", an interrupt request is generated each time one AD con-
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