TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 595

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

19.3.1.2
(1)
Backup Transition Flow
ROM or built-in RAM.
The preparation program for changing to the backup mode must be executed in the built-in flash
Preparing for BACKUP mode
1. Stopping peripherals and saving data
2. Prohibit the interrupt
3. Setting of port keep function (CGSTBYCR<PTKEEP>)
4. Clock related setting and warm up time
DMAC, SMC and WDT. In case of transition to BACKUP SLEEP mode, no need to stop pe-
ripheral functions (CEC, RMC, RTC and KWUP) which are used in BACKUP SLEEP
mode. It is necessary to save data to preserved in BACKUP RAM. BACKUP RAM is
used only 8KB data from 0x2000_E000 to 0x2000_FFFF.
ble if needed. It is note that NMI interrupt and INTRTC interrupt request cannot be disa-
bled so that these interrupt requests must be avoided in advance.
is set to "1". Object ports are A to H, K, O, P, SWDIO, NMI. Port keep function is capa-
ble of retaining input enable / disable, port 0 / 1 output status and on / off status of pull-
up / pull-down register.
can hold the port status. When using the port keep function, port register of each port must
be set properly.
less the port keep function. The interrupt of BACKUP mode is set by using these ports.
by CGSYSCR<GEAR[2:0]>="000". Using BACKUP SLEEP is needed for starting low-
speed oscillator by CGOSCCR<XTEN>.
CGOSCCR<WUPT[11:0]><WUPTL[2:0]>. The warm up time is referred to the section
"Clock / Mode control".
Both in the NORMAL mode and SLOW mode stop peripheral function including
To prevent from obstruction a transition to BACKUP mode, interrupt request set to disa-
Port keep function retains the port status of the momentary when CGSTBCR<PTKEEP>
By these settings made before the transition to the BACKUP mode, port keep function
The input / output status of port I, J, L, M and N are depend on the port register regard-
All unnecessary ports must be set to disable by the input enable control register.
Stop PLL circuit by setting CGOSCCR<PLLON>="0". Set high-speed clock to fc (1/1)
In addition, it is necessary to setting warm up time returning from BACKUP mode by
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