TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 597

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

Stop peripheral function
Stop peripherals if needed.
Save backup data
Save data to BACKUP RAM if needed.
Disabling interrupt
So as not to obstruct the transiton to BACKUP mode,
interrupts is disabled if needed.
Setting port keep function
If CGSTBYCR<PTKEEP>=” 1” ,
retain port status of spectic port.
Setting warm up time
Set warm up time after returning from BACKUP mode
Setting clock gear
Stop PLL then set clock gear to fc (1/1).
Setting BACKUP mode
Set BACKUP SLEEP mode or BACKUP STOP mode
by CGSTBYCR<STBY>
Setting releasing source and change to BACKUP mode
Enable interrupt signal to permit the interruption,
and perform WFI instruction.
19.3.1.3
Transition Flowchart
Normal Operation
Figure 19-3 Stare transition flowchart
Page 573
Check CGRSTFLG register
Check if the reset operation made by returning BACKUP.
Perform interrupt setting
Jump to handler.
Check the BACKUP mode releasing source.
Port setting
Each port is setting the preceding status
before BACKUP mode.
Releasing port keep status
If CGSTBYCR<PTKEEP>=” 0” ,
releasing the specific port status.
Power-on shutdonw block
Start high-speed / low-speed oscillation
Start warm up timer operation
Reset releasing
Shutdown power suppy in the main block
NORMAL Operation
Waiting for the interrupt
TMPM362F10FG
Interrupt occurs