TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 420

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

12.11
Receive
12.11
12.11.1
12.11.2
12.11.3
12.11.2.1
12.11.2.2
12.11.3.1
bol is sampled at the seventh, eighth, and ninth pulses. From these three samples, majority logic is applied to
decide the received data.
Receive
The receive counter is a 4-bit binary counter and is up-counted by SIOCLK.
In the UART mode, sixteen SIOCLK clock pulses are used in receiving a single data bit and the data sym-
of the shift clock outputted to the SCLK pin.
the rising or falling edge of SCLK input signal depending on the SCxCR <SCLKS> setting.
when a normal start bit is detected.
ed, the interrupt INTTRX is generated.
fer full flag (SCxMOD2<RBFLL>) is set to "1". The receive buffer full flag is "0" cleared by reading the
receive buffer. The receive buffer flag does not have any value for the single buffer.
Receive Counter
Receive Control Unit
Receive Operation
In the SCLK output mode with SCxCR <IOC> set to "0", the RXD pin is sampled on the rising edge
In the SCLK input mode with SCxCR <IOC> set to "1", the serial receive data RXD pin is sampled on
The receive control unit has a start bit detection circuit, which is used to initiate receive operation
The received data is stored by 1 bit in the receive shift register. When a complete set of bits has been stor-
When the double buffer is enabled, the data is moved to the receive buffer (SCxBUF) and the receive buf-
I/O interface mode
UART Mode
Receive Buffer
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TMPM362F10FG