TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 20

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

16. Remote control signal preprocessor(RMC)
17. Watchdog Timer(WDT)
18. Key-on Wakeup
xii
16.1 Basic operation....................................................................................................................523
16.2 Block Diagram.....................................................................................................................523
16.3 Registers..............................................................................................................................524
16.4 Operation Description.........................................................................................................537
17.1 Configuration.......................................................................................................................547
17.2 Register................................................................................................................................548
17.3 Operations............................................................................................................................550
17.4 Operation when malfunction (runaway) is detected...........................................................551
17.5 Control register....................................................................................................................553
18.1 Outline.................................................................................................................................555
18.2 Block Diagram.....................................................................................................................555
16.1.1
16.3.1
16.3.2
16.3.3
16.3.4
16.3.5
16.3.6
16.3.7
16.3.8
16.3.9
16.3.10
16.3.11
16.3.12
16.3.13
16.3.14
16.3.15
16.4.1
17.2.1
17.2.2
17.3.1
17.3.2
17.4.1
17.4.2
17.5.1
17.5.2
17.5.3
16.4.1.1
16.4.1.2
16.4.1.3
16.4.1.4
16.4.1.5
16.4.1.6
16.4.1.7
16.4.1.8
17.5.3.1
17.5.3.2
17.5.3.3
17.5.3.4
Reception of Remote Control Signal............................................................................................................................523
Register List...................................................................................................................................................................524
RMCxEN(Enable Register)...........................................................................................................................................525
RMCxREN(Receive Enable Register)..........................................................................................................................526
RMCxRBUF1(Receive Data Buffer Register 1)..........................................................................................................527
RMCxRBUF2(Receive Data Buffer Register 2)..........................................................................................................527
RMCxRBUF3(Receive Data Buffer Register 3)..........................................................................................................528
RMCxRCR1(Receive Control Register 1)....................................................................................................................529
RMCxRCR2(Receive Control Register 2) ..................................................................................................................530
RMCxRCR3(Receive Control Register 3) ..................................................................................................................531
Reception of Remote Control Signal............................................................................................................................537
WDMOD(Watchdog Timer Mode Register) ...............................................................................................................548
WDCR (Watchdog Timer Control Register)................................................................................................................549
Basic Operation.............................................................................................................................................................550
Operation Mode and Status...........................................................................................................................................550
INTWDT interrupt generation.......................................................................................................................................551
Internal reset generation................................................................................................................................................552
Watchdog Timer Mode Register (WDMOD)...............................................................................................................553
Watchdog Timer Control Register(WDCR).................................................................................................................553
Setting example.............................................................................................................................................................554
RMCxRCR4(Receive Control Register 4) ................................................................................................................532
RMCxRSTAT(Receive Status Register) ...................................................................................................................533
RMCxEND1(Receive End bit Number Register 1) ..................................................................................................534
RMCxEND2(Receive End bit Number Register 2) ..................................................................................................534
RMCxEND3(Receive End bit Number Register 3) ..................................................................................................535
RMCxFSSEL(Source Clock selection Register) .......................................................................................................536
Sampling clock
Basic operation
Preparation
Enabling Reception
Stopping Reception
Receiving Remote Control Signal without Leader in Waiting Leader
A Leader only with Low Width
Receiving a Remote Control Signal in a Phase Method
Disabling control
Enabling control
Watchdog timer clearing control
Detection time of watchdog timer