TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 72
TMPM362F10FG
Manufacturer Part Number
TMPM362F10FG
Description
32BIT MICROCONTROLLER
Manufacturer
Toshiba
Series
TX03r
Datasheet
1.TMPM362F10FG.pdf
(744 pages)
Specifications of TMPM362F10FG
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, Microwire, SIO, SPI, SSP, UART/USART
Peripherals
DMA, WDT
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b
Package / Case
144-LQFP
Processor Series
TX03
Core
ARM Cortex M3
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
1024K
Rom Type
Flash
Ram (kbytes)
64K
Number Of Pins
144
Package
LQFP(20x20)
Vcc
3V
Cpu Mhz
64
Ssp (ch) Spi
1
I2c/sio (ch)
5
Uart/sio (ch)
12
Usb
-
Can
-
Ethernet
-
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
16
12-bit Ad Converter
-
16-bit Timer / Counter
16
Motor / Igbt Control
-
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
-
Clock Gear
Y
Low-power Hold Function
Y
Remote Control Interface
Y
Hardware Cec Controller
Y
Comparators
-
Low-voltage Detector
-
Etm Hardware Trace
4-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Number Of I /o
-
Eeprom Size
-
Oscillator Type
-
Lead Free Status / Rohs Status
Details
Other names
Q5704184A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMPM362F10FG
Manufacturer:
Freescale
Quantity:
488
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6.3
Clock control
6.3.7
6.3.8
Note 1: The phase difference (AC timing) between the system clock output by the SCOUT and the internal clock is not guaran-
Note 2: Before switching to BACKUP SLEEP, CGSTBYCR<PTKEEP> should beset to "1".
er, the "fperiph" clock specified in the CGSYSCR<FPSEL0> can be divided according to the setting in the
CGSYSCR<PRCK[2:0]>. After the controller is reset, fperiph/1 is selected as φT0.
speed clock fs, the system clock fsys and fsys/2, and the prescaler input clock for peripheral I/O φT0. The out-
put clock is selected by setting the CGSYSCR<SCOSEL[1:0]>.
Table 6-4 SCOUT Output Status in Each Mode
Prescaler Clock Control
System Clock Pin Output Function
Each peripheral function has a prescaler for dividing a clock. As the clock φT0 to be input to each prescal-
TMPM362F10FG enables to output the system clock from a pin. The SCOUT pin can output the low
Table 6-4 shows the pin status in each mode when the SCOUT pin is set to the SCOUT output.
SCOUT selection
CGSYSCR
Note:To use the clock gear, ensure that you make the time setting such that prescaler output φTn from
<SCOSEL[1:0]> = "00"
<SCOSEL[1:0]> = "01"
<SCOSEL[1:0]> = "10"
<SCOSEL[1:0]> = "11"
teed.
each peripheral function is slower than fsys (φTn < fsys). Do not switch the clock gear while the tim-
er counter or other peripheral function is operating.
Mode
Output the φT0
NORMAL
clock
Output the fsys/2 clock
Output the fsys clock
SLOW
Page 48
Output the fs clock
IDLE2,1
Fixed "0" or "1"
Low power consumption mode
SLEEP
STOP/BACKUP
TMPM362F10FG
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