TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 496

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

14.6
Data Transfer Procedure in the I2C Bus ModeI2C
14.6.4
14.6.5
SBIxCR2
to start a sequence for generating the stop condition on the bus.
a slave device.The procedure of generating a restart in the master mode is described below.
SDAx pin is held at the "High" level and the SCLx pin is released. Because no stop condition is generated
on the bus, other devices recognize that the bus is busy.
line to the "Low" level.
in "14.6.2 Generating the Start Condition and a Slave Address"to generate the start condition.
the software after the bus is determined to be free.
Note 1: Do not write <MST> to "0" when it is "0". (Restart cannot be initiated.)
Note 2: When the master device is acting as a receiver, data transmission from the slave device which
When SBIxSR<BB> is "1", writing "1" to SBIxCR2<MST, TRX, PIN> and "0" to <BB> causes the SBI
Do not alter the contents of <MST, TRX, BB, PIN> until the stop condition appears on the bus.
If another device is holding down the SCL bus line, the SBI waits until the SCL line is released.
After that, the SDA pin goes "High", causing the stop condition to be generated.
Restart is used when a master device changes the data transfer direction without terminating the transfer to
First, write SBIxCR2<MST, TRX, BB> to "0" and write "1" to <PIN> to release the bus. At this time, the
Then, test SBIxSR<BB> and wait until it becomes "0" to ensure that the SCLx pin is released.
Next, test <LRB> and wait until it becomes "1" to ensure that no other device is pulling the SCLx bus
Once the bus is determined to be free by following the above procedures, follow the procedures described
To satisfy the setup time of restart, at least 4.7μs wait period (in the standard mode) must be created by
Generating the Stop Condition
Restart Procedure
←
serves as a transmitter must be completed before generating a restart. To complete data trans-
fer, slave device must receive a "High" level acknowledge signal. For this reason, <LBR> before
generating a restart becomes "1", the rising edge of the SCL line is not detected even <LBR>=
7
1
6
1
Figure 14-13 Generating the Stop Condition
"1"→<MST>
"1"→<TRX>
"0"→<BB>
"1"→<PIN>
SCLx pin
SDAx pin
<PIN>
<BB>(Read)
5
0
4
1
3
1
2
0
1
0
0
0
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Generates the stop condition.
Stop condition
TMPM362F10FG