TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 641

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

21.4
21.4.1
21.4.2
The RTC incorporates a second counter that generates a 1Hz signal from a 32.768 kHz signal.
The second counter operation must be taken into account when using the RTC.
Operational Description
A carry during writing ruins correct data writing. The following procedure ensures the correct data writing.
Reading clock data
Writing clock data
1. Using 1Hz interrupt
2. Using pair reading
1. Using 1 Hz interrupt
2. Resetting counter
ry during reading. To ensure correct data reading, read the clock data twice as shown below. A
pair of data read successively needs to match.
data is written in the time between 1Hz interrupt and subsequent one second count, it completes cor-
rectly.
The 1Hz interrupt is generated being synchronized with counting up of the second counter.
Data can be read correctly if reading data after 1Hz interrupt occurred.
There is a possibility that the clock data may be read incorrectly if the internal counter operates car-
The 1Hz interrupt is generated by being synchronized with counting up of the second counter. If
Write data after resetting the second counter.
The 1Hz-interrupt is generated one second after enabling the interrupt subsequent to counter reset.
Figure 21-2 Flowchart of the clock data reading
RTCPAGER<PAGE> = "0",
then select PAGE0
Clock data reading
Clock data reading
1st data = 2nd data
(2nd)
Start
(1st)
Page 617
End
YES
NO
TMPM362F10FG