TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 22

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

21. Real Time Clock (RTC)
22. Flash
xiv
21.1 Function...............................................................................................................................607
21.2 Block Diagram.....................................................................................................................607
21.3 Detailed Description Register.............................................................................................608
21.4 Operational Description.......................................................................................................617
21.5 Alarm function.....................................................................................................................620
22.1 Flash Memory......................................................................................................................623
22.2 Operation Mode...................................................................................................................626
21.3.1
21.3.2
21.3.3
21.4.1
21.4.2
21.4.3
21.5.1
21.5.2
21.5.3
22.1.1
22.1.2
22.2.1
22.2.2
22.2.3
22.2.4
22.2.5
22.2.6
22.2.7
22.2.8
22.2.9
22.2.10
20.4.5.1
20.4.5.2
20.4.5.3
20.4.5.4
20.4.5.5
20.4.5.6
20.4.5.7
21.3.3.1
21.3.3.2
21.3.3.3
21.3.3.4
21.3.3.5
21.3.3.6
21.3.3.7
21.3.3.8
21.3.3.9
21.3.3.10
21.3.3.11
22.2.2.1
22.2.2.2
22.2.3.1
22.2.9.1
22.2.9.2
22.2.9.3
22.2.9.4
22.2.10.1
22.2.10.2
22.2.10.3
22.2.10.4
22.2.10.5
Register List...................................................................................................................................................................608
Control Register.............................................................................................................................................................608
Detailed Description of Control Register.....................................................................................................................610
Reading clock data........................................................................................................................................................617
Writing clock data.........................................................................................................................................................617
Entering the Low Power Consumption Mode..............................................................................................................619
1Hz cycle "Low" pulse..................................................................................................................................................621
16Hz cycle "Low" pulse................................................................................................................................................621
Features..........................................................................................................................................................................623
Block Diagram of the Flash Memory Section..............................................................................................................625
Reset Operation.............................................................................................................................................................627
User Boot Mode (Single chip mode)............................................................................................................................627
Single Boot Mode..........................................................................................................................................................636
Configuration for Single Boot Mode............................................................................................................................639
Memory Map.................................................................................................................................................................639
Interface specification....................................................................................................................................................641
Data Transfer Format....................................................................................................................................................642
Restrictions on internal memories.................................................................................................................................642
Transfer Format for Boot Program...............................................................................................................................642
"Low" pulse (when the alarm register corresponds with the clock)...........................................................................620
Operation of Boot Program.........................................................................................................................................649
Starting AD Conversion
AD Conversion
Top-priority AD conversion during normal AD conversion
Stopping Repeat Conversion Mode
Reactivating normal AD conversion
Conversion completion
Interrupt generation timings and AD conversion result storage register
RTCSECR (Second column register (for PAGE0 only))
RTCMINR (Minute column register (PAGE0/1))
RTCHOURR (Hour column register(PAGE0/1))
RTCDAYR (Day of the week column register(PAGE0/1))
RTCDATER (Day column register (for PAGE0/1 only))
RTCMONTHR (Month column register (for PAGE0 only))
RTCMONTHR (Selection of 24-hour clock or 12-hour clock (for PAGE1 only))
RTCYEARR (Year column register (for PAGE0 only))
RTCYEARR (Leap year register (for PAGE1 only))
(1-A) Method 1: Storing a Programming Routine in the Flash Memory
(1-B) Method 2: Transferring a Programming Routine from an External Host
(2-A) Using the Program in the On-Chip Boot ROM
RAM Transfer
Show Flash Memory SUM
Transfer Format for the Show Product Information
Chip Erase and Protect Bit Erase
RTCPAGER(PAGE register(PAGE0/1))
RTCRESTR (Reset register (for PAGE0/1))
RAM Transfer Command
Show Flash Memory SUM Command
Show Product Information Command
Chip and Protection Bit Erase Command
Acknowledge Responses