TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 323

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

9.5.2
ing a set of Linked Lists first.
transfer of successive data. Each time DMA transfer is complete, the next LLI setting will be loaded to contin-
ue the DMA operation (Daisy Chain).
Linked list operation
+C
To operate the scatter/gather function, a transfer source and source data areas need to be defined by creat-
Each setting is called LLI (LinkedList).
Each LLI controls the transfer of one block of data. Each LLI indicates normal DMA setting and controls
An example of the setting is shown below.
When transferring data in the area enclosed by the square.
+0
+4
+8
1. The first DMA transfer setting should be made directly in the DMA register.
2. The second and subsequent DMA transfer settings should be written in the addresses of the memo-
3. To stop up to N'th DMA transfer, set "next LLI AddressX" to 0x0000_0000.
ry set in "next LLI AddressX."
Directly programmed
into the DMA registers
Source Address1
Destination Address1
Next LLI Address2
Control register value
Transfer source
memory image
0x0C000
0x0A000
0x0B000
0x002000
Source Address2
Destination Address2
Next LLI Address3
Control register value
LLI address2
Page 299
0x00E000
Destination memory
image
LLI addressN
Source AddressN
Destination AddressN
0x00000000
Control register value
TMPM362F10FG